FPGA-Based Interface of Digital DAQ System for Double-Scattering Compton Camera
10.1007/s13139-018-0551-8
- Author:
Soo Mee KIM
1
;
Young Soo KIM
Author Information
1. Maritime ICT R&D Center, Korea Institute of Ocean Science & Technology, 385 Haeyang-ro, Yeongdo-gu, Busan 49111, South Korea. smeekim@kiost.ac.kr
- Publication Type:Original Article
- Keywords:
Double-scattering Compton camera (DSCC);
Prompt gamma imaging;
FPGA-based digital DAQ system;
Sync calibration of interface between ADC and FPGA
- MeSH:
Calibration;
Logic
- From:Korean Journal of Nuclear Medicine
2018;52(6):430-437
- CountryRepublic of Korea
- Language:English
-
Abstract:
PURPOSE: The double-scattering Compton camera (DSCC) is a radiation imaging system that can provide both unknown source energy spectra and 3D spatial source distributions. The energies and detection locations measured in coincidence with three CdZnTe (CZT) detectors contribute to reconstructing emission energies and a spatial image based on conical surface integrals. In this study, we developed a digital data acquisition (DAQ) board to support our research into coincidence detection in the DSCC.METHODS: The main components of the digital DAQ board were 12 ADCs and one field programmable gate array (FPGA). The ADCs digitized the analog 96-channel CZTsignals at a sampling rate of 50MHz and transferred the serialized ADC samples and the bit and frame clocks to the FPGA. In order to correctly capture the ADC sample bits in the FPGA, we conducted individual sync calibrations for all the ADC channels to align the bit and frame clocks to the right positions of the ADC sample bits. The FPGA logic design was composed of IDELAYand IDDR components, six shift registers, and bit slip buffer resources.RESULTS: Using a Deskew test pattern, the delay value of the IDELAY component was determined to align the bit clock to the center of each sample bit.We determined the bit slip in the 12-bit ADC sample using an MSB test pattern by checking where the MSB value of one is located in the captured parallel data.CONCLUSION: After sync calibration, we tested the interface between the ADCs and the FPGA with a synthetic analog Gaussian signal. The 96 ADC channels yielded a mean R2 goodness-of-fit value of 0.95 between the Gaussian curve and the captured 12-bit parallel data.
